数字设计和计算机体系结构 英文版2025|PDF|Epub|mobi|kindle电子书版本百度云盘下载

数字设计和计算机体系结构 英文版PDF格式电子书版下载

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Chapter 1 From Zero to One3

1.1 The Game Plan3

1.2 The Art of Managing Complexity4

1.2.1 Abstraction4

1.2.2 Discipline5

1.2.3 The Three-Y's6

1.3 The Digital Abstraction7

1.4 Number Systems9

1.4.1 Decimal Numbers9

1.4.2 Binary Numbers9

1.4.3 Hexadecimal Numbers11

1.4.4 Bytes,Nibbles,and All That Jazz13

1.4.5 Binary Addition14

1.4.6 Signed Binary Numbers15

1.5 Logic Gates19

1.5.1 NOT Gate20

1.5.2 Buffer20

1.5.3 AND Gate20

1.5.4 OR Gate21

1.5.5 Other Two-Input Gates21

1.5.6 Multiple-Input Gates21

1.6 Beneath the Digital Abstraction22

1.6.1 Supply Voltage22

1.6.2 Logic Levels22

1.6.3 Noise Margins23

1.6.4 DC Transfer Characteristics23

1.6.5 The Static Discipline24

1.7 CMOS Transistors26

1.7.1 Semiconductors27

1.7.2 Diodes27

1.7.3 Capacitors28

1.7.4 nMOS and pMOS Transistors28

1.7.5 CMOS NOT Gate31

1.7.6 Other CMOS Logic Gates31

1.7.7 Transmission Gates33

1.7.8 Pseudo-nMOS Logic33

1.8 Power Consumption34

1.9 Summary and a Look Ahead35

Exercises37

Interview Questions48

Chapter 2 Combinational Logic Design51

2.1+ Introduction51

2.2 Boolean Equations54

2.2.1 Terminology54

2.2.2 Sum-of-Products Form54

2.2.3 Product-of-Sums Form56

2.3 Boolean Algebra56

2.3.1 Axioms57

2.3.2 Theorems of One Variable57

2.3.3 Theorems of Several Variables58

2.3.4 The Truth Behind It All60

2.3.5 Simplifying Equations61

2.4 From Logic to Gates62

2.5 Multilevel Combinational Logic65

2.5.1 Hardware Reduction66

2.5.2 Bubble Pushing67

2.6 X's and Z's,Oh My69

2.6.1 Illegal Value：X69

2.6.2 Floating Value：Z70

2.7 Karnaugh Maps71

2.7.1 Circular Thinking73

2.7.2 Logic Minimization with K-Maps73

2.7.3 Don't Cares77

2.7.4 The Big Picture78

2.8 Combinational Building Blocks79

2.8.1 Multiplexers79

2.8.2 Decoders82

2.9 Timing84

2.9.1 Propagation and Contamination Delay84

2.9.2 Glitches88

2.10 Summary91

Exercises93

Interview Questions100

Chapter 3 Sequential Logic Design103

3.1 Introduction103

3.2 Latches and Flip-Flops103

3.2.1 SR Latch105

3.2.2 D Latch107

3.2.3 D Flip-Flop108

3.2.4 Register108

3.2.5 Enabled Flip-Flop109

3.2.6 Resettable Flip-Flop110

3.2.7 Transistor-Level Latch and Flip-Flop Designs110

3.2.8 Putting It All Together112

3.3 Synchronous Logic Design113

3.3.1 Some Problematic Circuits113

3.3.2 Synchronous Sequential Circuits114

3.3.3 Synchronous and Asynchronous Circuits116

3.4 Finite State Machines117

3.4.1 FSM Design Example117

3.4.2 State Encodings123

3.4.3 Moore and Mealy Machines126

3.4.4 Factoring State Machines129

3.4.5 FSM Review132

3.5 Timing of Sequential Logic133

3.5.1 The Dynamic Discipline134

3.5.2 System Timing135

3.5.3 Clock Skew140

3.5.4 Metastability143

3.5.5 Synchronizers144

3.5.6 Derivation of Resolution Time146

3.6 Parallelism149

3.7 Summary153

Exercises155

Interview Questions165

Chapter 4 Hardware Description Languages167

4.1 Introduction167

4.1.1 Modules167

4.1.2 Language Origins168

4.1.3 Simulation and Synthesis169

4.2 Combinational Logic171

4.2.1 Bitwise Operators171

4.2.2 Comments and White Space174

4.2.3 Reduction Operators174

4.2.4 Conditional Assignment175

4.2.5 Internal Variables176

4.2.6 Precedence178

4.2.7 Numbers179

4.2.8 Z's and X's179

4.2.9 Bit Swizzling182

4.2.10 Delays182

4.2.11 VHDL Libraries and Types183

4.3 Structural Modeling185

4.4 Sequential Logic190

4.4.1 Registers190

4.4.2 Resettable Registers191

4.4.3 Enabled Registers193

4.4.4 Multiple Registers194

4.4.5 Latches195

4.5 More Combinational Logic195

4.5.1 Case Statements198

4.5.2 If Statements199

4.5.3 Verilog casez201

4.5.4 Blocking and Nonblocking Assignments201

4.6 Finite State Machines206

4.7 Parameterized Modules211

4.8 Testbenches214

4.9 Summary218

Exercises219

Interview Questions230

Chapter 5 Digital Building Blocks233

5.1 Introduction233

5.2 Arithmetic Circuits233

5.2.1 Addition233

5.2.2 Subtraction240

5.2.3 Comparators240

5.2.4 ALU242

5.2.5 Shifters and Rotators244

5.2.6 Multiplication246

5.2.7 Division247

5.2.8 Further Reading248

5.3 Number Systems249

5.3.1 Fixed-Point Number Systems249

5.3.2 Floating-Point Number Systems250

5.4 Sequential Building Blocks254

5.4.1 Counters254

5.4.2 Shift Registers255

5.5 Memory Arrays257

5.5.1 Overview257

5.5.2 Dynamic Random Access Memory260

5.5.3 Static Random Access Memory260

5.5.4 Area and Delay261

5.5.5 Register Files261

5.5.6 Read Only Memory262

5.5.7 Logic Using Memory Arrays264

5.5.8 Memory HDL264

5.6 Logic Arrays266

5.6.1 Programmable Logic Array266

5.6.2 Field Programmable Gate Array268

5.6.3 Array Implementations273

5.7 Summary274

Exercises276

Interview Questions286

Chapter 6 Architecture289

6.1 Introduction289

6.2 Assembly Language290

6.2.1 Instructions290

6.2.2 Operands：Registers,Memory,and Constants292

6.3 Machine Language299

6.3.1 R-type Instructions299

6.3.2 I-type Instructions301

6.3.3 J-type Instructions302

6.3.4 Interpreting Machine Language Code302

6.3.5 The Power of The Stored Program303

6.4 Programming304

6.4.1 Arithmetic/Logical Instructions304

6.4.2 Branching308

6.4.3 Conditional Statements310

6.4.4 Getting Loopy311

6.4.5 Arrays314

6.4.6 Procedure Calls319

6.5 Addressing Modes327

6.6 Lights,Camera,Action：Compiling,Assembling,and Loading330

6.6.1 The Memory Map330

6.6.2 Translating and Starting a Program331

6.7 Odds and Ends336

6.7.1+ Pseudoinstructions336

6.7.2 Exceptions337

6.7.3 Signed and Unsigned Instructions338

6.7.4 Floating-Point Instructions340

6.8 Real-World Perspective：IA-32 Architecture341

6.8.1 M-32 Registers342

6.8.2 M-32 Operands342

6.8.3 Status Flags344

6.8.4 IA-32 Instructions344

6.8.5 M-32 Instruction Encoding346

6.8.6 Other IA-32 Peculiarities348

6.8.7 The Big Picture349

6.9 Summary349

Exercises351

Interview Questions361

Chapter 7 Microarchitecture363

7.1 Introduction363

7.1.1 Architectural State and Instruction Set363

7.1.2 Design Process364

7.1.3 MIPS Microarchitectures366

7.2 Performance Analysis366

7.3 Single-Cycle Processor368

7.3.1 Single-Cycle Datapath368

7.3.2 Single-Cycle Control374

7.3.3+ More Instructions377

7.3.4 Performance Analysis380

7.4 Multicycle Processor381

7.4.1 Multicycle Datapath382

7.4.2 Multicycle Control388

7.4.3 More Instructions395

7.4.4 Performance Analysis397

7.5 Pipelined Processor401

7.5.1 Pipelined Datapath404

7.5.2 Pipelined Control405

7.5.3 Hazards406

7.5.4 More Instructions418

7.5.5 Performance Analysis418

7.6 HDL Representation421

7.6.1 Single-Cycle Processor422

7.6.2 Generic Building Blocks426

7.6.3 Testbench428

7.7 Exceptions431

7.8 Advanced Microarchitecture435

7.8.1 Deep Pipelines435

7.8.2 Branch Predicuon437

7.8.3 Superscalar Processor438

7.8.4 Out-of-Order Processor441

7.8.5 Register Renaming443

7.8.6 Single Instruction Multiple Data445

7.8.7 Multithreading446

7.8.8 Multiprocessors447

7.9 Real-World Perspective：IA-32 Microarchitecture447

7.10 Summary453

Exercises455

Interview Questions461

Chapter 8 Memory Systems463

8.1 Introduction463

8.2 Memory System Performance Analysis467

8.3 Caches468

8.3.1 What Data Is Held in the Cache?469

8.3.2 How Is the Data Found?470

8.3.3 What Data Is Replaced?478

8.3.4 Advanced Cache Design479

8.3.5 The Evolution of MIPS Caches483

8.4 Virtual Memory484

8.4.1 Address Translation486

8.4.2 The Page Table488

8.4.3 The Translation Lookaside Buffer490

8.4.4 Memory Protection491

8.4.5 Replacement Policies492

8.4.6 Multilevel Page Tables492

8.5 Memory-Mapped I/O494

8.6 Real-World Perspective：IA-32 Memory and I/O Systems499

8.6.1 IA-32 Cache Systems499

8.6.2 M-32 Virtual Memory501

8.6.3 IA-32 Programmed I/O502

8.7 Summary502

Exercises504

Interview Questions512

Appendix A Digital System Implementation515

A.1 Introduction515

A.2 74xx Logic515

A.2.1 Logic Gares516

A.2.2 Other Functions516

A.3 Programmable Logic516

A.3.1 PROMs516

A.3.2 PLAs520

A.3.3 FPGAs521

A.4 Application-Specific Integrated Circuits523

A.5 Data Sheets523

A.6 Logic Families529

A.7 Packaging and Assembly531

A.8 Transmission lines534

A.8.1 Matched Termination536

A.8.2 Open Termination538

A.8.3 Short Termination539

A.8.4 Mismatched Termination539

A.8.5 When to Use Transmission Line Models542

A.8.6 Proper Transmission Line Terminations542

A.8.7 Derivation of Z0544

A.8.8 Derivation of the Reflection Coefficient545

A.8.9 Putting It All Together546

A.9 Economics547

Appendix B MIPS Instructions551

Further Reading555

Index557