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1.1 The Digital Age1

Chapter 1 Introduction1

1.2 Analog and Digital Representations of Information2

1.3 The Digital Computer2

9.4 The Primitive Flow Table3

9.5 Reduction of Input-Restricted Flow Tables3

9.5.1 Determination of Compatible Pairs of States3

9.5.2 Dctermination of Maximal Compatibles3

9.5.3 Determination of Minimal Collections of Maximal Compatible Sets9.5.4 Constructing the Minimal-Row Flow Table9.6 A General Procedure to Flow Table Reduction9.6.1 Reducing the Number of Stable States9.6.2 Merging the Rows of a Primitive Flow3

9.4.1 The Primitive Flow Table for Example 9.3

1.3.1 The Organization of a Digital Computer3

9.7.2 The Transition Table for Example 9.4

9.4.2 The Primitive Flow Table for Example 9.4

1.4 An Overview5

1.3.2 The Operation of a Digital Computer5

2.1 Positional Number Systems7

Chapter 2 Number Systems,Arithmetic,and Codes7

2.2 Counting in a Positional Number System9

2.3 Basic Arithmetic Operations11

2.3.2 Subtraction11

2.3.1 Addition11

2.3.3 Multiplication14

2.4 Polynomial Method of Number Conversion16

2.3.4 Division16

2.5 Iterative Method of Number Conversion19

2.5.1 Iterative Method for Converting Integers20

2.5.2 Verification of the Iterative Method for Integers21

2.5.3 Iterative Method for Converting Fractions22

2.5.5 A Final Example23

2.5.4 Verification of the Iterative Method for Fractions23

2.6 Special Conversion Procedures24

2.7 Signed Numbers and Complements26

2.8 Addition and Subtraction with r's-Complements31

2.8.1 Signed Addition and Subtraction33

2.9.1 Signed Addition and Subtraction36

2.10 Codes36

2.9 Addition and Subtraction with(r-1)'s-Complements36

2.10.1 Decimal Codes37

2.10.2 Unit-Distance Codes40

2.10.3 Alphanumeric Codes42

2.11 Error Detection43

Problems45

2.12 Error Correction45

2.12.3 Check Sum Digits for Error Correction45

2.12.2 Single-Error Correction plus Double-Error Detection45

2.12.1 Hamming Code45

Chapter 3 Boolean Algebra and Combinational Networks53

3.1 Definition of a Boolean Algebra54

3.1.1 Principle of Duality55

3.2 Boolean Algebra Theorems55

3.3 A Two-Valued Boolean Algebra62

3.4 Boolean Formulas and Functions65

3.4.1 Normal Formulas67

3.5 Canonical Formulas68

3.5.1 Minterm Canonical Formulas68

3.5.2 m-Notation70

3.5.3 Maxterm Canonical Formulas72

3.5.4 M-Notation73

3.6.1 Equation Complementation75

3.6 Manipulations of Boolean Formulas75

3.6.2 Expansion about a Variable76

3.6.3 Equation Simplification76

3.6.4 The Reduction Theorems78

3.6.5 Minterm Canonical Formulas79

3.6.6 Maxterm Canonical Formulas80

3.6.7 Complements of Canonical Formulas81

3.7 Gates and Combinational Networks83

3.7.2 Combinational Networks84

3.7.1 Gates84

3.7.3 Analysis Procedure85

3.7.4 Synthesis Procedure86

3.7.5 A Logic Design Example87

3.8 Incomplete Boolean Functions and Don't-Care Conditions89

3.8.1 Describing Incomplete Boolean Functions91

3.8.2 Don't-Care Conditions in Logic Design91

3.9 Additional Boolean Operations and Gates93

3.9.1 The Nand-Function94

3.9.3 Universal Gates95

3.9.2 The Nor-Function95

3.9.4 Nand-Gate Realizations97

3.9.5 Nor-Gate Realizations100

3.9.6 The Exclusive-Or-Function103

3.10 Gate Properties105

3.9.7 The Exclusive-Nor-Function105

3.10.1 Noise Margins107

3.10.2 Fan-Out108

3.10.3 Propagation Delays109

Problems110

3.10.4 Power Dissipation110

4.1 Formulation of the Simplification Problem119

Chapter 4 Simplification of Boolean Expressions119

4.1.1 Criteria of Minimality120

4.1.2 The Simplification Problem121

4.2 Prime Implicants and Irredundant Disjunctive Expressions121

4.2.1 Implies121

4.2.2 Subsumes122

4.2.3 Implicants and Prime Implicants123

4.2.4 Irredundant Disjunctive Normal Formulas125

4.3 Prime Implicates and Irredundant Conjunctive Expressions125

4.4.1 One-Variable and Two-Variable Maps127

4.4 Karnaugh Maps127

4.4.2 Three-Variable and Four-Variable Maps128

4.4.3 Karnaugh Maps and Canonical Formulas130

4.4.4 Product and Sum Tern Representations on Karnaugh Maps133

4.5.1 Prime Implicants and Karnaugh Maps137

4.5 Using Karnaugh Maps to Obtain Minimal Expressions for Complete Boolean Functions137

4.5.2 Essential Prime Implicants142

4.5.3 Minimal Sums143

4.5.4 Minimal Products147

4.6 Minimal Expressions of Incomplete Boolean Functions149

4.6.1 Minimal Sums150

4.6.2 Minimal Products151

4.7.2 Six-Variable Maps152

4.7 Five-Variable and Six-Variable Karnaugh Maps152

4.7.1 Five-Variable Maps152

4.8 The Quine-McCluskey Method of Generating Prime Implicants and Prime Implicates4.8.1 Prime Implicants and the Quine-McCluskey Method4.8.2 Algorithm for Generating Prime Implicants4.8.3 Prime Implicates and the Quine-McCluskey Method4.9 Prime-Impl152

Chapter 5 Logic Design with MSI Components and Programmable Logic Devices160

5.1　Binary Adders and Subtracters161

5.1.1 Binary Subtracters163

5.1.2 Carry Lookahead Adder166

5.1.3 Large High-Speed Adders Using the Carry Lookahead Principle168

5.2 Decimal Adders172

5.3 Comparators176

5.4 Decoders178

5.4.1 Logic Design Using Decoders179

5.4.2 Decoders with an Enable Input186

5.5 Encoders190

5.6 Multiplexers192

5.6.1 Logic Design with Multiplexers196

5.7 Programmable Logic Devices(PLDs)206

5.7.1 PLD Notation209

5.8 Programmable Read-Only Memories(PROMs)209

5.9 Programmable Logic Arrays(PLAs)213

5.10 Programmable Array Logic(PAL)Devices222

Problems224

Chapter 6 Flip-Flops and Simpie Flip-Flop Applications231

6.1 The Basic Bistable Element232

6.2 Latches233

6.2.1 The SR Latch234

6.2.2 An Application of the SR Latch:A Switch Debouncer235

6.2.3 The SR Latch237

6.2.4 The Gated SR Latch238

6.2.5 The Gated D Latch239

6.3 Timing Considerations240

6.3.1 Propagation Delays240

6.3.2 Minimum Pulse Width242

6.3.3 Setup and Hold Times242

6.4 Master-Slave Flip-Flops(Pulse-Triggered Flip-Flops)243

6.4.1 The Master-Slave SR Flip-Flop244

6.4.2 The Master-Slave JK Flip-Flop247

6.4.3 0's and 1's Catching249

6.4.4 Additional Types of Master-Slave Flip-Flops250

6.5.1 The Positive-Edge-Triggered D Flip-Flop251

6.5 Edge-Triggered Flip-Flops251

6.5.2 Negative-Edge-Triggered D Flip-Flops254

6.5.3 Asynchronous Inputs254

6.5.4 Additional Types of Edge-Triggered Flip-Flops256

6.5.5 Master-Slave Flip-Flops with Data Lockout258

6.6 Characteristic Equations259

6.7 Registers262

6.8.1 Binary Ripple Counters267

6.8 Counters267

6.8.2 Synchronous Binary Counters270

6.8.3 Counters Based on Shift Registers275

6.9 Design of Synchronous Counters277

6.9.1 Design of a Synchronous Mod-6 Counter Using Clocked JK Flip-Flops278

6.9.2 Design of a Synchronous Mod-6 Counter Using Clocked D,T,or SR Flip-Flops282

6.9.3 Self-Correcting Counters286

Problems288

Chapter 7 Synchronous Sequential Networks297

7.1 Structure and Operation of Clocked Synchronous Sequential Networks298

7.2 Analysis of Clocked Synchronous Sequential Networks301

7.2.1 Excitation and Output Expressions303

7.2.2 Transition Equations304

7.2.3 Transition Tables305

7.2.4 Excitation Tables307

7.2.5 State Tables309

7.2.6 State Diagrams310

7.2.7 Network Terminal Behavior312

7.3 Modeling Clocked Synchronous Sequential Network Behavior315

7.3.1 The Serial Binary Adder as a Mealy Network315

7.3.2 The Serial Binary Adder as a Moore Network318

7.3.3 A Sequence Recognizer320

7.3.4 A 0110/1001 Sequence Recognizer323

7.3.5 A Final Example326

7.4 State Table Reduction328

7.4.1 Determining Equivalent Pairs of States329

7.4.2 Obtaining the Equivalence Classes of States335

7.4.3 Constructing the Minimal State Table336

7.4.4 The 0110/1001 Sequence Recognizer340

7.5 The State Assignment345

7.5.1 Some Simple Guidelines for Obtaining State Assignments348

7.5.2 Unused States352

7.6 Completing the Design of Clocked Synchronous Sequential Networks354

7.6.1 Realizations Using Programmable Logic Devices362

Problcms366

Chapter 8 Algorithmic State Machines374

8.1 The Algorithmic State Machine374

8.2 ASM Charts377

8.2.1 The State Box378

8.2.2 The Decision Box379

8.2.4 ASM Blocks380

8.2.3 The Conditional Output Box380

8.2.5 ASM Charts386

8.2.6 RelationshiP between State Diagrams and ASM Charts389

8.3.1 A Sequence Recognizer391

8.3 Two Examples of Synchronous Sequential Network Design Using ASM Charts391

8.3.2 A Parallel(Unsigned)Binary Multiplier393

8.4 State Assignments398

8.5 ASM Tables400

8.5.1 ASM Transition Tables400

8.5.2 Assigned ASM Transition Tables402

8.5.3 Algebraic Representation of Assigned Transition Tables405

8.5.4 ASM Excitation Tables407

8.6.1 Realizations Using Discrete Gates409

8.6 ASM Realizations409

8.6.2 Realizations Using Multiplexers414

8.6.3 Realizations Using PLAs417

8.6.4 Realizations Using PROMs420

8.7 Asynchronous Inputs421

Problems423

Chapter 9 Asynchronous Sequential Networks435

9.1 Structure and Operation of Asynchronous Sequential Networks436

9.2 Analysis of Asynchronous Sequential Networks440

9.2.1 The Excitation Table442

9.2.2 The Transition Table444

9.2.3 The State Table446

9.2.4 The Flow Table447

9.2.5 The Flow Diagram449

9.3 Races in Asynchronous Sequential Networks450

9.7.3 The Need for Additional State Variables452

9.7.4 A Systematic State-Assignment Procedure452

9.8 Completing the Asynchronous Sequential Network Design452

9.9 Static and Dynamic Hazards in Combinational Networks452

9.9.1 Static Hazards453

9.9.2 Detecting Static Hazards455

9.9.3 Eliminating Static Hazards459

9.9.4 Dynamic Hazards461

9.9.6 Hazards in Asynchronous Networks Involving Latches462

9.9.5 Hazard-Free Combinational Logic Networks462

9.10 Essential Hazards464

9.10.1 Example of an Essential Hazard465

9.10.2 Detection of Essential Hazards466

Problems469

Bibliography480

翻译版目录483

第1章 绪论483

1.1 数字时代483

1.2 信息的模拟和数字表示484

1.3 数字计算机484

1.3.1 数字计算机的结构485

1.3.2 数字计算机的操作486

1.4 概述487

第2章 数制系统，算术和编码488

2.1 位置数制系统488

2.2 位置数制系统中的计数490

2.3 基本算术操作491

2.3.1 加法491

2.3.2 减法493

2.3.3 乘法494

2.3.4 除法496

2.4 数制转换的多项式法496

2.5 数制转换的迭代法499

2.5.1 整数转换的迭代法499

2.5.3 小数转换的迭代法500

2.5.2 整数迭代法的证明500

2.5.4 小数迭代法的证明501

2.5.5 最后举例501

2.6 特殊转换过程502

2.7 有符号数和补数503

2.8 r补数的加法和减法507

2.9 r-1补数的加法和减法511

2.10 编码511

2.10.1 十进制编码511

2.10.2 单位距离编码514

2.10.3 字符编码516

2.11 错误检测517

第3章 布尔代数和组合网络519

3.1 布尔代数的定义520

3.2 布尔代数诸定理521

3.3 二值布尔代数527

3.4 布尔公式和函数529

3.5 规范公式531

3.5.1 最小项规范公式532

3.5.2 m标记533

3.5.3 最大项规范公式534

3.5.4 M标记535

3.6 布尔公式的处理537

3.6.1 方程求补537

3.6.2 变量扩展538

3.6.3 方程化简539

3.6.4 简化定理540

3.6.5 最小项规范公式541

3.6.6 最大项规范公式542

3.6.7 规范公式的反函数543

3.7 门和组合网络544

3.7.1 门545

3.7.2 组合网络545

3.7.3 分析过程546

3.7.4 综合过程547

3.7.5 逻辑设计实例548

3.8 不完全确定布尔函数和无关条件549

3.8.2 逻辑设计中的无关项条件551

3.8.1 描述不完全确定布尔函数551

3.9 其他布尔运算和门553

3.9.1 与非函数553

3.9.2 或非函数554

3.9.3 通用门555

3.9.4 与非门实现556

3.9.5 或非门实现559

3.9.6 异或函数561

3.9.7 异或非函数563

3.10 门特性563

3.10.1 噪声容限564

3.10.4 功耗566

3.10.2 扇出566

3.10.3 传输延时566

第4章 布尔表达式的化简567

4.1 化简问题的表述567

4.1.1 最简化的准则567

4.1.2 化简问题568

4.2 质蕴含项和非冗余析取表达式569

4.2.1 蕴含569

4.2.2 包含570

4.2.3 蕴含项和质蕴含项570

4.2.4 非冗余析取正则表达式572

4.3 质包含项和非冗余合取表达式572

4.4 卡诺图573

4.4.1 单变量和两变量卡诺图574

4.4.2 三变量和四变量卡诺图574

4.4.3 卡诺图和规范公式577

4.4.4 卡诺图中与项和或项的表示578

4.5 使用卡诺图得到完全确定布尔函数的最简表达式583

4.5.1 质蕴含项和卡诺图583

4.5.2 基本质蕴含项586

4.5.3 最简或形式587

4.5.4 最简与形式590

4.6 不完全确定布尔函数的最简表达式592

4.6.1 最简或形式592

4.6.2 最简与形式593

第5章 使用MSI元件和可编程逻辑器件的逻辑设计595

5.1 二进制加法器和减法器596

5.1.1 二进制减法器598

5.1.2 超前进位加法器600

5.1.3 利用超前进位原理实现大型高速加法器602

5.2 十进制加法器606

5.3 比较器609

5.4 译码器612

5.4.1 使用译码器的逻辑设计612

5.4.2 有使能输入的译码器619

5.5 编码器622

5.6 复用器623

5.7 可编程逻辑器件635

5.8 可编程只读存储器638

5.9 可编程逻辑阵列641

5.10 可编程阵列逻辑器件649

第6章 触发器及其简单应用652

6.1 双稳态基本单元653

6.2 锁存器654

6.2.1 SR锁存器654

6.2.2 一种SR锁存器的应用：开关去反弹器656

6.2.3 SR锁存器657

6.2.4 门控SR锁存器658

6.2.5 门控D锁存器659

6.3.1 传输延时660

6.3 触发器时序的考虑660

6.3.2 最小脉冲宽度662

6.3.3 建立和保持时间662

6.4 主从触发器663

6.4.1 主从型SR触发器664

6.4.2 主从型JK触发器666

6.4.3 0信号和1信号的捕获669

6.4.4 其他类型的主从型触发器670

6.5 边沿触发的触发器671

6.5.1 正边沿触发D触发器671

6.5.2 负边沿触发D触发器673

6.5.3 异步输入信号674

6.5.4 其他类型的边沿触发的触发器675

6.5.5 具有数据锁存功能的主从型触发器677

6.6 特征方程678

6.7 寄存器680

6.8 计数器685

6.8.1 二进制逐次进位计数器685

6.8.2 同步二进制计数器687

6.8.3 基于移位寄存器的计数器692

6.9 同步计数器的设计693

6.9.1 用钟控JK触发器设计模6同步计数器694

6.9.2 使用钟控D、T以及SR触发器的模6同步计数器的设计698

6.9.3 自启动的计数器701

第7章 同步时序网络703

7.1 钟控同步时序网络的结构和操作过程704

7.2 钟控同步时序网络的分析706

7.2.1 激励和输出方程708

7.2.2 转换方程708

7.2.3 转换表709

7.2.4 激励表711

7.2.5 状态表712

7.2.6 状态图713

7.2.7 网络的最终行为714

7.3 钟控同步时序网络的行为的建模716

7.3.1 米利型串行二进制加法器717

7.3.2 摩尔型串行二进制加法器719

7.3.3 序列检测器720

7.3.4 0110/1001序列检测器722

7.3.5 总结举例725

7.4 状态表的化简726

7.4.1 确定等价状态对727

7.4.2 获得等价状态类732

7.4.3 建立最小状态表733

7.4.4 0110/1001序列检测器736

7.5 状态分配741

7.5.1 状态分配的一些简单指导原则744

7.5.2 未用状态747

7.6 完成钟控同步时序网络的设计749

附录A 中英文名词索引760