模拟电路版图的艺术 第2版 英文版2025|PDF|Epub|mobi|kindle电子书版本百度云盘下载

模拟电路版图的艺术 第2版 英文版PDF格式电子书版下载

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1 Device Physics1

1.1 Semiconductors1

1.1.1. Generation and Recombination4

1.1.2. Extrinsic Semiconductors6

1.1.3. Diffusion and Drift9

1.2 PN Junctions11

1.2.1. Depletion Regions11

1.2.2. PNDiodes13

1.2.3. Schottky Diodes16

1.2.4. Zener Diodes18

1.2.5. Ohmic Contacts19

1.3 Bipolar Junction Transistors21

1.3.1. Beta23

1.3.2. I-V Characteristics24

1.4 MOS Transistors25

1.4.1. Threshold Voltage27

1.4.2. I-V Characteristics29

1.5 JFET Transistors32

1.6 Summary34

1.7 Exercises35

2 Semiconductor Fabrication37

2.1 Silicon Manufacture37

2.1.1. Crystal Growth38

2.1.2. Wafer Manufacturing39

2.1.3. The Crystal Structure of Silicon39

2.2 Photolithography41

2.2.1. Photoresists41

2.2.2. Photomasks and Reticles42

2.2.3. Patterning43

2.3 Oxide Growth and Removal43

2.3.1. Oxide Growth and Deposition44

2.3.2. Oxide Removal45

2.3.3. Other Effects of Oxide Growth and Removal47

2.3.4. Local Oxidation of Silicon (LOCOS)49

2.4 Diffusion and Ion Implantation50

2.4.1. Diffusion51

2.4.2. Other Effects of Diffusion53

2.4.3. Ion Implantation55

2.5 Silicon Deposition and Etching57

2.5.1. Epitaxy57

2.5.2. Polysilicon Deposition59

2.5.3. Dielectric Isolation60

2.6 Metallization62

2.6.1. Deposition and Removal of Aluminum63

2.6.2. Refractory Barrier Metal65

2.6.3. Silicidation67

2.6.4. Interlevel Oxide, Interlevel Nitride, and Protective Overcoat69

2.6.5. Copper Metallization71

2.7 Assembly73

2.7.1. Mount and Bond74

2.7.2. Packaging77

2.8 . Summary78

2.9 Exercises78

3 Representative Processes80

3.1 Standard Bipolar81

3.1.1. Essential Features81

3.1.2. Fabrication Sequence82

Starting Material82

N-Buried Layer82

Epitaxial Growth83

Isolation Diffusion83

Deep-N+83

Base Implant84

Emitter Diffusion84

Contact85

Metallization85

Protective Overcoat86

3.1.3. Available Devices86

NPN Transistors86

PNP Transistors88

Resistors90

Capacitors92

3.1.4. Process Extensions93

Up-Down Isolation93

Double-Level Metal94

Schottky Diodes94

High-Sheet Resistors94

Super-Beta Transistors96

3.2 Polysilicon-Gate CMOS96

3.2.1. Essential Features97

3.2.2. Fabrication Sequence98

Starting Material98

Epitaxial Growth98

N-Well Diffusion98

Inverse Moat99

Channel Stop Implants100

LOCOS Processing and Dummy Gate Oxidation100

Threshold Adjust101

Polysilicon Deposition and Patterning102

Source/Drain Implants102

Contacts103

Metallization103

Protective Overcoat103

3.2.3. Available Devices104

NMOS Transistors104

PMOS Transistors106

Substrate PNP Transistors107

Resistors107

Capacitors109

3.2.4. Process Extensions109

Double-Level Metal110

Shallow Trench Isolation110

Silicidation111

Lightly Doped Drain (LDD) Transistors112

Extended-Drain, High-Voltage Transistors113

3.3 Analog BiCMOS114

3.3.1. Essential Features115

3.3.2. Fabrication Sequence116

Starting Material116

N-Buried Layer116

Epitaxial Growth117

N-Well Diffusion and Deep-N+117

Base Implant118

Inverse Moat118

Channel Stop Implants119

LOCOS Processing and Dummy Gate Oxidation119

Threshold Adjust119

Polysilicon Deposition and Pattern120

Source/Drain Implants120

Metallization and Protective Overcoat120

Process Comparison121

3.3.3. Available Devices121

NPN Transistors121

PNP Transistors123

Resistors125

3.3.4. Process Extensions125

Advanced Metal Systems126

Dielectric Isolation126

3.4 Summary130

3.5 Exercises131

4 Failure Mechanisms133

4.1 ElectricalOverstress133

4.1.1. Electrostatic Discharge (ESD)134

Effects135

Preventative Measures135

4.1.2. Electromigration136

Effects136

Preventative Measures137

4.1.3. Dielectric Breakdown138

Effects138

Preventative Measures139

4.1.4. The Antenna Effect141

Effects141

Preventative Measures142

4.2 Contamination143

4.2.1. Dry Corrosion144

Effects144

Preventative Measures145

4.2.2. Mobile Ion Contamination145

Effects145

Preventative Measures146

4.3 Surface Effects148

4.3.1. Hot Carrier Injection148

Effects148

Preventative Measures150

4.3.2. ZenerWalkout151

Effects151

Preventative Measures152

4.3.3. Avalanche-Induced Beta Degradation153

Effects153

Preventative Measures154

4.3.4. Negative Bias Temperature Instability154

Effects155

Preventative Measures155

4.3.5. Parasitic Channels and Charge Spreading156

Effects156

Preventative Measures (Standard Bipolar)159

Preventative Measures (CMOS and BiCMOS)162

4.4 Parasitics164

4.4.1. Substrate Debiasing165

Effects166

Preventative Measures167

4.4.2. Minority-Carrier Injection169

Effects169

Preventative Measures (Substrate Injection)172

Preventative Measures (Cross-Injection)178

4.4.3. Substrate Influence180

Effects180

Preventative Measures180

4.5 Summary183

4.6 Exercises183

5 Resistors185

5.1 Resistivity and Sheet Resistance185

5.2 Resistor Layout187

5.3 Resistor Variability191

5.3.1. Process Variation191

5.3.2. Temperature Variation192

5.3.3. Nonlinearity193

5.3.4. Contact Resistance196

5.4 Resistor Parasitics197

5.5 Comparison of Available Resistors200

5.5.1. Base Resistors200

5.5.2. Emitter Resistors201

5.5.3. Base Pinch Resistors202

5.5.4. High-Sheet Resistors202

5.5.5. EpiPinch Resistors205

5.5.6. Metal Resistors206

5.5.7. Poly Resistors208

5.5.8. NSD and PSD Resistors211

5.5.9. N-Well Resistors211

5.5.10. Thin-Film Resistors212

5.6 Adjusting Resistor Values213

5.6.1. Tweaking Resistors213

Sliding Contacts214

Sliding Heads215

Trombone Slides215

Metal Options215

5.6.2. Trimming Resistors216

Fuses216

Zener Zaps219

EPROM Trims221

Laser Trims222

5.7 Summary223

5.8 Exercises224

6 Capacitors and Inductors226

6.1 Capacitance226

6.1.1. Capacitor Variability232

Process Variation232

Voltage Modulation and Temperature Variation233

6.1.2. Capacitor Parasitics235

6.1.3. Comparison of Available Capacitors237

Base-Emitter Junction Capacitors237

MOS Capacitors239

Poly-Poly Capacitors241

Stack Capacitors243

Lateral Flux Capacitors245

High-Permittivity Capacitors246

6.2 Inductance246

6.2.1. Inductor Parasitics248

6.2.2. Inductor Construction250

Guidelines for lntegrating Inductors251

6.3 Summary252

6.4 Exercises253

7 Matching of Resistors and Capacitors254

7.1 Measuring Mismatch254

7.2 Causes of Mismatch257

7.2.1. Random Variation257

Capacitors258

Resistors258

7.2.2. Process Biases260

7.2.3. Interconnection Parasitics261

7.2.4. Pattern Shift263

7.2.5. Etch Rate Variations265

7.2.6. Photolithographic Effects267

7.2.7. Diffusion Interactions268

7.2.8. Hydrogenation270

7.2.9. Mechanical Stress and Package Shift271

7.2.10. Stress Gradients274

Piezoresistivity274

Gradients and Centroids275

Common-Centroid Layout277

Location and Orientation281

7.2.11. Temperature Gradients and Thermoelectrics283

Thermal Gradients285

Thermoelectric Effects287

7.2.12. Electrostatic Interactions288

Voltage Modulation288

Charge Spreading292

Dielectric Polarization293

Dielectric Relaxation294

7.3 Rules for Device Matching295

7.3.1. Rules for Resistor Matching296

7.3.2. Rules for Capacitor Matching300

7.4 Summary303

7.5 Exercises304

8 Bipolar Transistors306

8.1 Topics in Bipolar Transistor Operation306

8.1.1. Beta Rolloff308

8.1.2. Avalanche Breakdown308

8.1.3. Thermal Runaway and Secondary Breakdown310

8.1.4. Saturation in NPN Transistors312

8.1.5. Saturation in Lateral PNP Transistors315

8.1.6. Parasitics of Bipolar Transistors318

8.2 Standard Bipolar Small-Signal Transistors320

8.2.1. The Standard Bipolar NPN Transistor320

Construction of Small-Signal NPN Transistors322

8.2.2. The Standard Bipolar Substrate PNP Transistor326

Construction of Small-Signal Substrate PNP Transistors328

8.2.3. The Standard Bipolar Lateral PNP Transistor330

Construction of Small-Signal Lateral PNP Transistors332

8.2.4. High-Voltage Bipolar Transistors337

8.2.5. Super-Beta NPN Transistors340

8.3 CMOS and BiCMOS Small-Signal Bipolar Transistors341

8.3.1. CMOS PNPTransistors341

8.3.2. Shallow-Well Transistors345

8.3.3. Analog BiCMOS Bipolar Transistors347

8.3.4. Fast Bipolar Transistors349

8.3.5. Polysilicon-Emitter Transistors351

8.3.6. Oxide-IsolatedTransistors354

8.3.7. Silicon-Germanium Transistors356

8.4 Summary358

8.5 Exercises358

9 Applications of Bipolar Transistors360

9.1 Power Bipolar Transistors361

9.1.1. Failure Mechanisms of NPN Power Transistors362

Emitter Debiasing362

Thermal Runaway and Secondary Breakdown364

Kirk Effect366

9.1.2. Layout of Power NPN Transistors368

The Interdigitated-Emitter Transistor369

The Wide-Emitter Narrow-Contact Transistor371

The Christmas-Tree Device372

The Cruciform-Emitter Transistor373

Power Transistor Layout in Analog BiCMOS374

Selecting a Power Transistor Layout376

9.1.3. Power PNP Transistors376

9.1.4. Saturation Detection and Limiting378

9.2 Matching Bipolar Transistors381

9.2.1. Random Variations382

9.2.2. Emitter Degeneration384

9.2.3. NBLShadow386

9.2.4. Thermal Gradients387

9.2.5. Stress Gradients391

9.2.6. Filler-Induced Stress393

9.2.7. Other Causes of Systomatic Mismatch395

9.3 Rules for Bipolar Transistor Matching396

9.3.1. Rules for Matching Vertical Transistors397

9.3.2. Rules for Matching Lateral Transistors402

9.4 Summary402

9.5 Exercises403

10 Diodes406

10.1 Diodes in Standard Bipolar406

10.1.1. Diode-ConnectedTransistors406

10.1.2. Zener Diodes409

Surface Zener Diodes410

Buried Zeners412

10.1.3. Schottky Diodes415

10.1.4. Power Diodes420

10.2 Diodes in CMOS and BiCMOS Processes422

10.2.1. CMOS Junction Diodes422

10.2.2. CMOS and BiCMOS Schottky Diodes423

10.3 Matching Diodes425

10.3.1. Matching PN Junction Diodes425

10.3.2. Matching Zener Diodes426

10.3.3. Matching Schottky Diodes428

10.4 Summary428

10.5 Exercises429

11 Field-Effect Transistors430

11.1 Topics in MOS Transistor Operation431

11.1.1. Modeling the MOSTransistor431

Device Transconductance432

Threshold Voltage434

11.1.2. Parasitics of MOS Transistors438

Breakdown Mechanisms440

CMOS Latchup442

Leakage Mechanisms443

11.2 Constructing CMOS Transistors446

11.2.1. Coding the MOS Transistor447

Width and Length448

11.2.2. N-Well and P-Well Processes449

11.2.3. Channel Stop Implants452

11.2.4. Threshold Adjust Implants453

11.2.5. Scaling the Transistor456

11.2.6. Variant Structures459

Serpentine Transistors461

Annular Transistors462

11.2.7. Backgate Contacts464

11.3 Floating-GateTransistors467

11.3.1. Principles of Floating-Gate Transistor Operation469

11.3.2. Single-Poly EEPROM Memory472

11.4 The JFET Transistor474

11.4.1. Modeling the JFET474

11.4.2. JFETLayout476

11.5 Summary479

11.6 Exercises479

12 Applications of MOS Transistors482

12.1 Extended-Voltage Transistors482

12.1.1. LDD and DDDTransistors483

12.1.2. Extended-Drain Transistors486

Extended-Drain NMOS Transistors487

Extended-Drain PMOS Transistors488

12.1.3. Multiple Gate Oxides489

12.2 Power MOSTransistors491

12.2.1. MOS Safe Operating Area492

Electrical SOA493

Electrothermal SOA496

Rapid Transient Overload497

12.2.2. Conventional MOS Power Transistors498

The Rectangular Device499

The Diagonal Device500

Computation of RM501

Other Considerations502

Nonconventional Structures503

12.2.3. DMOSTransistors505

The Lateral DMOS Transistor506

RESURF Transistors508

The DMOS NPN510

12.3 MOSTransistor Matching511

12.3.1. Geometric Effects513

Gate Area513

Gate Oxide Thickness514

Channel Length Modulation515

Orientation515

12.3.2. Diffusion and Etch Effects516

Polysilicon Etch Rate Variations516

Diffusion Penetration of Polysilicon517

Contacts Over Active Gate518

Diffusions Near the Channel518

PMOS versus NMOS Transistors519

12.3.3. Hydrogenation520

Fill Metal and MOS Matching521

12.3.4. Thermal and Stress Effects521

Oxide Thickness Gradients522

Stress Gradients522

Thermal Gradients522

12.3.5. Common-Centroid Layout of MOSTransistors523

12.4 Rules for MOSTransistor Matching528

12.5 Summary531

12.6 Exercises531

13 Special Topics534

13.1 Merged Devices534

13.1.1. Flawed Device Mergers535

13.1.2. Successful Device Mergers539

13.1.3. Low-Risk Merged Devices541

13.1.4. Medium-Risk Merged Devices542

13.1.5. Devising New Merged Devices544

13.1.6. The Role of Merged Devices in Analog BiCMOS544

13.2 Guard Rings545

13.2.1. Standard Bipolar Electron Guard Rings546

13.2.2. Standard Bipolar Hole Guard Rings547

13.2.3. Guard Rings in CMOS and BiCMOS Designs548

13.3 Single-level Interconnection551

13.3.1. Mock Layouts and StickDiagrams551

13.3.2. Techniques for Crossing Leads553

13.3.3. Types of Tunnels555

13.4 Constructing the Padring557

13.4.1. Scribe Streets and Alignment Markers557

13.4.2. Bondpads, Trimpads, and Testpads558

13.5 ESD Structures562

13.5.1. Zener Clamp563

13.5.2. Two-Stage Zener Clamps565

13.5.3. Buffered Zener Clamp566

13.5.4. VCES Clamp568

13.5.5. VECS Clamp569

13.5.6. Antiparallel Diode Clamps570

13.5.7. Grounded-Gate NMOS Clamps570

13.5.8. CDM Clamps572

13.5.9. Lateral SCR Clamps573

13.5.10. Selecting ESD Structures575

13.6 Exercises578

14 Assembling the Die581

14.1 Die Planning581

14.1.1. Cell Area Estimation582

Resistors582

Capacitors582

Vertical Bipolar Transistors583

Lateral PNP Transistors583

MOS Transistors583

MOS Power Transistors584

Computing Cell Area584

14.1.2. Die Area Estimation584

14.1.3. Gross Profit Margin587

14.2 Floorplanning588

14.3 Top-Level Interconnection594

14.3.1. Principles of Channel Routing594

14.3.2. Special Routing Techniques596

Kelvin Connections597

Noisy Signals and Sensitive Signals598

14.3.3. Electromigration600

14.3.4. Minimizing Stress Effects603

14.4 Conclusion604

14.5 Exercises605

Appendices607

A. Table of Acronyms Used in the Text607

B. The Miller Indices of a Cubic Crystal611

C. Sample Layout Rules614

D. Mathematical Derivations622

E. Sources for Layout Editor Software627

Index628