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Computer organization and architecture designing for performance (Seventh Edition) = 计算机组织与结构 性能设计(第2025|PDF|Epub|mobi|kindle电子书版本百度云盘下载

Computer organization and architecture designing for performance (Seventh Edition) = 计算机组织与结构 性能设计(第
  • William Stallings 著
  • 出版社: Higher Education Press
  • ISBN:7040282542
  • 出版时间:2009
  • 标注页数:756页
  • 文件大小:126MB
  • 文件页数:787页
  • 主题词:计算机体系结构-教材-英文

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图书目录

PART ONE OVERVIEW1

Chapter 1 Introduction1

1.1 Organization and Architecture2

1.2 Structure and Function3

1.3 Why Study Computer Organization and Architecture?10

Chapter 2 Computer Evolution and Performance11

2.1 A Brief History of Computers12

2.2 Designing for Performance33

2.3 Pentium and PowerPC Evolution40

2.4 Recommended Reading43

2.5 Key Terms,Review Questions,and Problems44

PART TWO THE COMPUTER SYSTEM48

Chapter 3 A Top-Level View of Computer Function and Interconnection48

3.1 Computer Components50

3.2 Computer Function52

3.3 Interconnection Structures66

3.4 Bus Interconnection68

3.5 PCI77

3.6 Recommended Reading87

3.7 Key Terms,Review Questions,and Problems87

Appendix 3A Timing Diagrams91

Chapter 4 Cache Memory93

4.1 Computer Memory System Overview94

4.2 Cache Memory Principles101

4.3 Elements of Cache Design104

4.4 Pentium 4 and PowerPC Cache Organizations120

4.5 Recommended Reading124

4.6 Key Terms,Review Questions,and Problems125

Appendix 4A Performance Characteristics of Two-Level Memories128

Chapter 5 Internal Memory136

5.1 Semiconductor Main Memory137

5.2 Error Correction146

5.3 Advanced DRAM Organization151

5.4 Recommended Reading156

5.5 Key Terms,Review Questions,and Problems157

Chapter 6 External Memory161

6.1 Magnetic Disk162

6.2 RAID171

6.3 Optical Memory180

6.4 Magnetic Tape186

6.5 Recommended Reading188

6.6 Key Terms,Review Questions,and Problems189

Chapter 7 Input/Output192

7.1 External Devices194

7.2 I/O Modules198

7.3 Programmed I/O201

7.4 Interrupt-Driven I/O204

7.5 Direct Memory Access213

7.6 I/O Channels and Processors219

7.7 The External Interface:FireWire and InfiniBand221

7.8 Recommended Reading230

7.9 Key Terms,Review Questions,and Problems230

Chapter 8 Operating System Support233

8.1 Operating System Overview234

8.2 Scheduling245

8.3 Memory Management252

8.4 PentiumⅡ and PowerPC Memory Management263

8.5 Recommended Reading271

8.6 Key Terms,Review Questions,and Problems271

PART THREE THE CENTRAL PROCESSING UNIT275

Chapter 9 Computer Arithmetic275

9.1 The Arithmetic and Logic Unit276

9.2 Integer Representation277

9.3 Integer Arithmetic282

9.4 Floating-Point Representation298

9.5 Floating-Point Arithmetic303

9.6 Recommended Reading214

9.7 Key Terms,Review Questions,and Problems215

Chapter 10 Instruction Sets:Characteristics and Functions319

10.1 Machine Instruction Characteristics321

10.2 Types of Operands327

10.3 Pentium and PowerPC Data Types329

10.4 Types of Operations332

10.5 Pentium and PowerPC Operation Types344

10.6 Assembly Language354

10.7 Recommended Reading356

10.8 Key Terms,Review Questions,and Problems356

Appendix 10A Stacks362

Appendix 10B Little-,Big-,and Bi-Endian366

Chapter 11 Instruction Sets:Addressing Modes and Formats371

11.1 Addressing372

11.2 Pentium and PowerPC Addressing Modes379

11.3 Instruction Formats384

11.4 Pentium and PowerPC Instruction Formats392

11.5 Recommended Reading396

11.6 Key Terms,Review Questions,and Problems396

Chapter 12 Processor Structure and Function400

12.1 Processor Organization401

12.2 Register Organization403

12.3 Instruction Cycle408

12.4 Instruction Pipelining412

12.5 The Pentium Processor426

12.6 The PowerPC Processor434

12.7 Recommended Reading440

12.8 Key Terms,Review Questions,and Problems441

Chapter 13 Reduced Instruction Set Computers445

13.1 Instruction Execution Characteristics447

13.2 The Use of a Large Register File452

13.3 Compiler-Based Register Optimization457

13.4 Reduced Instruction Set Architecture459

13.5 RISC Pipelining465

13.6 MIPS R4000468

13.7 SPARC475

13.8 RISC versus CISC Controversy480

13.9 Recommended Reading481

13.10 Key Terms,Review Questions,and Problems482

Chapter 14 Instruction-Level Parallelism and Superscalar Processors485

14.1 Overview487

14.2 Design Issues491

14.3 Pentium500

14.4 PowerPC506

14.5 Recommended Reading514

14.6 Key Terms,Review Questions,and Problems515

Chapter 15 The IA-64 Architecture520

15.1 Motivation522

15.2 General Organization523

15.3 Predication,Speculation,and Software Pipelining525

15.4 IA-64 Instruction Set Architecture541

15.5 Itanium Organization547

15.6 Recommended Reading550

15.7 Key Terms,Review Questions,and Problems551

PART FOUR THE CONTROL UNIT554

Chapter 16 Control Unit Operation554

16.1 Micro-Operations556

16.2 Control of the Processor562

16.3 Hardwired Implementation574

16.4 Recommended Reading577

16.5 Key Terms,Review Questions,and Problems577

Chapter 17 Microprogrammed Control579

17.1 Basic Concepts580

17.2 Microinstruction Sequencing589

17.3 Microinstruction Execution595

17.4 TI 8800607

17.5 Recommended Reading617

17.6 Key Terms,Review Questions,and Problems618

PART FIVE PARALLEL ORGANIZATION620

Chapter 18 Parallel Processing620

18.1 Multiple Processor Organizations622

18.2 Symmetric Multiprocessors624

18.3 Cache Coherence and the MESI Protocol632

18.4 Multithreading and Chip Multiprocessors638

18.5 Clusters645

18.6 Nonuniform Memory Access651

18.7 Vector Computation655

18.8 Recommended Reading668

18.9 Key Terms,Review Questions,and Problems669

Appendix A Number Systems675

A.1 The Decimal System676

A.2 The Binary System676

A.3 Converting between Binary and Decimal677

A.4 Hexadecimal Notation679

A.5 Problems681

Appendix B Digital Logic682

B.1 Boolean Algebra683

B.2 Gates685

B.3 Combinational Circuits687

B.4 Sequential Circuits708

B.5 Recommended Reading717

B.6 Problems717

Appendix C Projects for Teaching Computer Organization and Architecture720

C.1 Research Projects721

C.2 Simulation Projects721

C.3 Reading/Report Assignments722

Glossary723

References733

Index745

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