嵌入式微控制器与处理器设计 英文版2025|PDF|Epub|mobi|kindle电子书版本百度云盘下载

嵌入式微控制器与处理器设计 英文版PDF格式电子书版下载

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CHAPTER 1 EMBEDDED PROCESSORS1

1.0 Microcontrollers1

1.1 Microcontroller Markets1

1.2 Data Path2

1.3 Commercial Microcontrollers2

1.4 SoC Core Processors2

1.5 Relative SoC Unit Volumes3

1.6 Very-Large-Scale Integration(VLSI)Chip Design Tools4

1.7 Intellectual Property4

1.8 Instruction Set Architecture6

1.9 Return on Investment6

1.10 Semiconductor Technology Developments7

CHAPTER 2 MICROCONTROLLER ARCHITECTURE11

2.0 Computer on a Chip11

2.1 John yon Neumann12

2.1.1 von Neumann Architecture12

2.2 Computer Architectures13

2.2.1 CISC and RISC13

2.3 Semiconductor Technology14

2.3.1 Small-Scale Integration14

2.3.2 Hardware Bus14

2.3.3 Intelligent Peripherals15

2.3.4 Standardized I/O Interfaces15

2.4 MSI and LSI16

2.5 Electronic Calculator17

2.5.1 Programmable Calculator17

2.6 Microprocessors18

2.6.1 Application-Oriented Processing18

2.6.2 Intel i400419

2.6.3 Intel i808019

2.7 Microprocessor Peripherals20

2.7.1 Microcomputer20

2.8 i8051 Microcontroller21

2.9 RISC Introduction22

2.9.1 RISC Processors22

2.9.2 RISC Synergy23

2.9.3 RISC Marketing24

2.10 Fabless Semiconductor Company24

2.10.1 RISC as Intellectual Property25

2.10.2 RISC Technology Curve25

2.11 Embedded Controller IP26

2.11.1 CISC IP27

2.11.2 RISC IP27

2.11.3 Third-Party IP27

2.12 Application Specific Processors27

2.13 Summary28

CHAPTER 3 EMBEDDED MICROCONTROLLER TECHNOLOGY30

3.0 Integrated Circuits30

3.1 Moore's Law30

3.1.1 Microprocessor Performance31

3.1.2 Enabling Technologies32

3.1.3 Amdahl's Law33

3.1.4 Technology Convergence33

3.2 Design Abstraction34

3.2.1 Instruction Set Architectures34

3.2.2 Processor Family Tree35

3.3 RISC and CISC35

3.3.1 Processor Technology36

3.3.2 Performance Measurement36

3.3.3 Program Instructions36

3.3.4 Cost per Instruction37

3.3.5 Microcoded Instructions37

3.4 Memory Technology38

3.4.1 Locality39

3.4.2 Memory Hierarchy39

3.4.3 Cache Memory40

3.4.4 L1 and L2 Cache40

3.4.5 Data Registers41

3.4.6 Instruction Queues41

3.4.7 Branch Instructions41

3.4.8 Memory Latency42

3.4.9 Cache Blocks42

3.5 Instruction Processing44

3.5.1 Symbolic Assembly44

3.5.2 Program Compilers45

3.5.3 Hard-Coded Instructions45

3.6 Program Design45

3.6.1 Program Code Size Creep46

3.6.2 CISC Instruction Set46

3.7 Unified Instruction Set47

3.7.1 Industry Standard Software47

3.7.2 Instruction Set Extensions47

3.8 RISC Instruction Set Architecture48

3.8.1 Microcode48

3.8.2 Micro Instruction Cycles48

3.8.3 Application Specific Instructions48

3.8.4 Single-Cycle Instructions49

3.9 Processor Logic49

3.9.1 Synchronous Logic50

3.9.2 Register Sets50

3.9.3 Orthogonal Registers50

3.9.4 Register Optimization50

3.9.5 Load/Store Data Operations51

3.10 Processor Functional Partitioning51

3.10.1 Instruction Pipelining51

3.10.2 Execution Units52

3.10.3 Pipeline Stages52

3.10.4 Pipeline Throughput53

3.10.5 Sequential Execution54

3.10.6 Branch Execution54

3.11 Five-Stage Pipeline54

3.11.1 Instruction Pipeline Stalls56

3.11.2 Branch Prediction Table56

3.11.3 Data Pipeline Stall56

3.12 Summary56

CHAPTER 4 MICROCONTROLLER FUNCTIONS58

4.0 Device Functions58

4.1 Transistor Technology59

4.1.1 CMOS Transistor59

4.1.2 CMOS Power Consumption60

4.1.3 Packaging60

4.1.4 Operating Temperature Range61

4.2 Memory Technologies61

4.2.1 DRAM62

4.2.2 SRAM62

4.2.3 NVRWM63

4.2.4 EEPROM63

4.2.5 FLASH Technology64

4.2.6 ROM64

4.3 Hardware Features64

4.3.1 Configuration Word64

4.3.2 Oscillator Types65

4.3.3 Reset66

4.3.4 Standby Modes66

4.3.5 Low-Power Consumption67

4.3.6 Watchdog Timer67

4.3.7 In-Circuit Programming67

4.4 Data Input/Output68

4.4.1 Parallel I/O68

4.4.2 Tri-State Bit I/O69

4.4.3 Memory Mapped I/O69

4.5 Synchronous Serial Communication70

CHAPTER 5 PROGRAM DESIGN72

5.0 Program Design72

5.1 Polling Program73

5.1.1 Program Flow73

5.1.2 Program Timing74

5.1.3 Sequential Tasks74

5.1.4 Task Timing75

5.1.5 Multiple Sequential Tasks76

5.2 Interrupts76

5.2.1 Asynchronous Timing77

5.2.2 Interrupt Enable77

5.2.3 Machine State78

5.2.4 Latency78

5.2.5 Context Switch79

5.2.6 Interrupt Vector79

5.2.7 Nested Interrupts80

5.2.8 Critical Code80

5.2.9 Interrupt Service Routine82

5.3 Real-Time Operating System82

5.4 Event-Driven System83

5.5 Nucleus83

5.6 System Layering84

5.7 Risk84

CHAPTER 6 HARDWARE/SOFTWARE DEBUG86

6.0 Hardware/Software Debug86

6.1 COTS Controller Tools87

6.2 Embedded Controller Tools88

6.3 First Silicon88

6.4 Bpard-Level Probes89

6.5 Debug Process Steps90

6.5.1 Software Editor90

6.5.2 Compilation91

6.5.3 Program Build92

6.5.4 Simulator92

6.5.5 In-Circuit Emulation93

6.6 SoC Debug Strategies94

6.6.1 SoC Software Debug95

6.6.2 Core-Level Debug95

6.6.3 JTAG/EJTAG Specification96

6.7 ARM SoC Debug96

6.8 MIPS SoC Debug98

6.8.1 EJTAG Functions99

CHAPTER 7 SERIAL DATA COMMUNICATIONS101

7.0 Serial Data Communication101

7.1 UART101

7.1.1 Asynchronous Mode102

7.1.2 Transmit/Receive Buffers104

7.2 SPI-Serial Peripheral Interface105

7.3 I2C-Inter-IC Bus108

7.3.1 How the I2C Bus Works109

7.3.2 I2C Bus Terminology110

7.3.3 Terminology for Bus Transfer111

7.4 CAN—Controller Area Network112

7.5 LIN—Local Interconnect Network115

7.6 I2S—Inter-IC Sound116

7.6.1 I2S Serial Data117

7.6.2 I2S Word Select117

7.6.3 I2S Bus Timing117

7.7 IrDA-Infrared Data Association118

7.7.1 IrDA Stack119

7.8 USB-Universal Peripheral Bus119

7.8.1 USB Topology120

7.8.2 USB Architecture121

7.8.3 USB Physical Connection122

7.8.4 USB Interface122

7.8.5 USB 2.0 Specification122

7.9 Bluetooth122

7.9.1 Bluetooth Architecture124

7.9.2 Bluetooth Frequency124

7.9.3 Bluetooth Network125

CHAPTER 8 ANALOG TO DIGITAL CONVERSION127

8.0 Analog-to-Digital Conversion127

8.1 Analog-to-Digital Conversion Overview127

8.2 Transducers129

8.3 Low-Pass Filter130

8.3.1 Active Filter131

8.4 Sampling131

8.5 Shannon's Sampling Theorem132

8.6 Whatis an ADC?133

8.6.1 ADC Converter Resolution134

8.6.2 LSB and MSB Defined134

8.6.3 Quantization135

8.6.4 Quantization Error137

8.6.5 Offset Error138

8.6.6 Differential Nonlinearity139

8.6.7 Missing Codes139

8.6.8 SNR—Signal-to-Noise Ratio140

8.7 Analog-to-Digital Conversion Algorithms141

8.7.1 Successive Approximation142

8.7.2 SAR ADC Architecture142

8.7.3 Flash ADC145

8.7.4 Integrating ADCs146

8.7.4.1 Single-Slope Architecture146

8.7.4.2 Dual-Slope Architecture147

8.7.5 Pipeline ADC148

8.7.6 Sigma-Delta149

8.8 Oversampling150

CHAPTER 9 DIGITAL SIGNAL PROCESSING153

9.0 Digital Signal Processing153

9.1 Whatis a DSP?154

9.1.1 Filtering and Synthesis155

9.1.2 DSP Performance155

9.1.3 Analog Signal Conversion156

9.2 DSP Controller Architectures156

9.3 Analog Filters159

9.3.1 Filter Performance Measurements159

9.3.2 Time Domain Response161

9.3.3 Analog Low-Pass Filter161

9.3.4 Active Analog Filters162

9.3.5 Active Filter Comparison163

9.4 Digital Filters164

9.4.1 Finite Input Response Filter164

9.4.2 FIR Filter Implementation166

9.4.3 Convolution167

9.4.4 Infinite Impulse Response Filter169

9.5 Signal Transformation170

9.5.1 Phasor Model170

9.5.2 Fourier Series171

9.5.3 Discrete Fourier Series171

9.5.4 Fourier Transform171

9.5.5 Discrete Fourier Transform172

9.6 Fast Fourier Transform174

9.6.1 FFT Implementation174

9.6.2 DFT"Butterfly"175

9.7 Table Addressing176

CHAPTER 10 FUZZY LOGIC178

10.0 Fuzzy Logic178

10.1 Fuzzy Logic Method180

10.2 Fuzzy Perception180

10.3 Fuzzy Logic Terminology181

10.4 Fuzzy Expert System182

10.4.1 The Inference Process183

10.4.2 Fuzzification183

10.4.3 Inference184

10.4.4 Composition184

10.4.5 Defuzzification185

10.5 Linguistic Variables185

10.5.1 Using Linguistic Variables187

10.5.2 Anatomy of a Fuzzy Rule188

10.5.3 Logically Combining Linguistic Variables188

10.6 PID Controller189

10.6.1 Linguistic Time of Day189

10.6.2 Linguistic Comparisons190

10.7 Fuzzy Logic Application191

10.7.1 How Fuzzy Logic is Used191

10.8 The Rule Matrix192

10.8.1 Fuzzy Logic Implementation193

10.8.2 Membership Functions194

10.8.3 Input Degree of Membership197

10.8.4 Inferencing197

10.9 Defuzzification198

10.9.1 Fuzzy Centroid Algorithm198

10.10 Tuning and System Enhancement199

CHAPTER 11 8-BIT MICROCONTROLLERS201

11.0 General-Purpose Microcontrollers201

11.1 MicroChip PIC18F4520202

11.1.1 PIC18F4520 Harvard Architecture202

11.1.2 Instruction Pipeline204

11.1.3 Special Features205

11.1.4 Power Management Modes205

11.1.5 Oscillator Configuration206

11.1.6 Reset207

11.1.7 Memory Organization208

11.1.8 Interrupt Structure210

11.1.9 Input/Output Ports211

11.1.10 Timer-Related Functions211

11.1.11 Timer Modules212

11.1.12 Capture/Compare/PWM Functions215

11.1.13 Serial Communication Interface218

11.1.13.1 MSSP218

11.1.13.2 SPI218

11.1.13.3 I2C219

11.1.13.4 EUSART220

11.1.14 Analog-to-Digital Converter222

11.1.15 Analog Comparator223

11.1.16 Special Features of the CPU224

11.1.17 Instruction Set225

11.1.18 Electrical Characteristics225

11.2 ZiLOG Z8 Encore! XP F0830 Series226

11.2.1 eZ8 CPU Description227

11.2.2 The Z8 Encore! CPU Architecture228

11.2.2.1 Fetch Unit228

11.2.2.2 Execution Unit228

11.2.3 Address Space229

11.2.3.1 Register File229

11.2.3.2 Program Memory230

11.2.3.3 Data Memory230

11.2.4 Peripherals Overview231

11.2.5 Reset Controller and Stop Mode Recovery233

11.2.6 Low-Power Modes233

11.2.7 General-Purpose Input/Output234

11.2.7.1 GPIO Architecture234

11.2.7.2 GPIO Altemate Functions235

11.2.7.3 GPIO Interrupts235

11.2.8 Interrupt Controller235

11.2.8.1 Master Interrupt Enable236

11.2.8.2 Interrupt Vectors and Priority236

11.2.9 Timers237

11.2.9.1 ONE-SHOT Mode237

11.2.9.2 CONTINUOUS Mode238

11.2.9.3 COMPARATOR COUNTER Mode238

11.2.9.4 PWM SINGLE OUTPUT Mode238

11.2.9.5 PWM DUAL OUTPUT Mode238

11.2.9.6 CAPTURE Mode239

11.2.9.7 CAPTURE RESTART Mode239

11.2.9.8 COMPARE Mode239

11.2.9.9 GATED Mode240

11.2.9.10 CAPTURE/COMPARE Mode240

11.2.10 Watchdog Timer240

11.2.11 Analog-to-Digital Converter241

11.2.11.1 ADC Operation242

11.2.11.2 ADC Timing242

11.2.12 Comparator243

11.2.13 Flash Memory243

11.2.14 Nonvolatile Data Storage243

11.2.15 On-Chip Debugger244

11.2.16 Oscillator Control245

11.2.16.1 Crystal Oscillator245

11.2.16.2 Internal Precision Oscillator246

11.2.17 eZ8 CPU Instructions and Programming247

11.2.17.1 Program Stack247

CHAPTER 12 16-BIT MICROCONTROLLER250

12.0 16-bit Processor Overview250

12.1 Freescale S12XD Processor Overview250

12.1.1 XGATE Overview253

12.1.1.1 XGATE Module254

12.1.1.2 XGATE RISC Core255

12.1.1.3 XGATE Programmer's Model255

12.1.1.4 XGATE Memory Map256

12.1.1.5 XGATE Semaphores257

12.1.1.6 XGATE Modes of Operation257

12.1.2 Clocking257

12.1.2.1 Clock and Reset Generator(CRG)258

12.1.2.2 Pierce Oscillator(XOSC)258

12.1.3 Analog-to-Digital Convertor(ATD)259

12.1.4 Enhanced Capture Timer(ECT)261

12.1.4.1 Features261

12.1.5 Pulse-Width Modulator(PWM)262

12.1.5.1 Features263

12.1.6 Interintegrated Circuit (IIC)263

12.1.6.1 Features263

12.1.7 Scalable Controller Area Network(CAN)264

12.1.7.1 Features264

12.1.7.2 CAN System265

12.1.8 Serial Communication Interface(SCI)265

12.1.8.1 Features265

12.1.8.2 Functional Description266

12.1.8.3 Data Formats268

12.1.8.4 Receiver268

12.1.8.5 Transmitter268

12.1.8.6 Baud Rate Generator268

12.1.9 Serial Peripheral Interface (SPI)269

12.19.1 Features269

12.19.2 Functional Description271

12.1.10 Periodic Interrupt Timer (PIT)272

12.1.10.1 Fealures273

12.1.11 Voltage Regulator(VREG)273

12.1.11.1 Features274

12.1.12 Background Debug Module(BDM)274

12.1.12.1 Features274

12.1.13 Interrupt Module(XINT)275

12.1.13.1 Features275

12.1.13.2 Interrupt Nesting276

12.1.14 Mapping Memory Control(MMC)277

12.1.14.1 Features277

12.1.15 Debug(DBG)278

12.1.15.1 Features278

12.1.16 External Bus Interface(XEBI)280

12.1.16.1 Features280

12.1.17 Port Integration Module(PIM)280

12.1.17.1 Features282

12.1.17.2 Port Pin282

12.1.17.3 Functional Description282

12.1.17.4 Data Register282

12.1.17.5 Input Register283

12.1.17.6 Data Direction Register283

12.1.18.2 Kbyte EEPROM(EETX2K)284

12.1.18.1 Features284

12.1.18.2 Functional Description285

12.1.18.3 EEPROM Module Security286

12.1.19 512 Kbyte Flash Module(FTX512K4)286

12.1.19.1 Features286

12.1.20 Security(SEC)286

12.1.20.1 Features286

12.1.20.2 Modes of Operation288

12.1.20.3 Secured Microcontroller288

12.2 Texas Instruments MSP430TM Family288

12.2.1 Low Power Design291

12.2.2 Flexible Clock System291

12.2.3 MSP430 CPU292

12.2.4 Operating Modes293

12.2.5 FLL+Clock Module293

12.2.6 Flash Memory Controller295

12.2.7 Hardware Multiplier295

12.2.8 DMA Controller296

12.2.9 Digital I/O297

12.2.10 Watchdog Timer297

12.2.11 Timers A and B298

12.2.12 USART299

12.2.13 USCI301

12.2.13.1 UART Mode301

12.2.13.2 SPI Mode301

12.2.13.3 I2C Mode303

12.2.14 ADC12 Function304

12.2.15 DAC12306

12.2.16 Embedded Emulation Module306

12.2.16.1 Triggers307

CHAPTER 13 INTELLECTUAL PROPERTY SoC CORES309

13.0 SoC Overview309

13.1 SoC Design Challenges310

13.1.1 Configurable Processors312

13.1.2 SoC Integration314

13.1.3 Extensible Processors316

13.1.4 Extensible Processors as RTL Alternatives316

13.1.5 Explicit Control Scheme317

13.2 The M1PS32 4K Processor Core Family318

13.2.1 Key Features of the 4KE Family319

13.2.2 Execution Unit322

13.2.3 Multiply/Divide Unit(MDU)323

13.2.4 Memory Manage Unit(MMU)324

13.2.5 Cache Controller325

13.2.6 Bus Interface Unit(BIU)325

13.2.7 Power Management326

13.2.8 Instruction Cache326

13.2.9 Data Cache327

13.2.10 EJTAG Controller327

13.2.11 System Coprocessor328

13.2.12 User-Defined Instructions(UDI)329

13.2.13 Instruction Pipeline329

13.2.13.1 Instruction Fetch329

13.2.13.2 Execution329

13.2.13.3 Memory Fetch330

13.2.13.4 Align330

13.2.13.5 Writeback330

13.2.14 Instruction Cache Miss330

13.2.15 Data Cache Miss331

13.2.16 Multiply/Divide Operations331

13.2.17 Branch Delay332

13.2.18 Memory Management332

13.2.18.1 MMU Overview332

13.2.19 Modes of Operation333

13.2.19.1 Virtual Memory Segments333

13.2.19.2 Uset Mode334

13.2.19.3 Kernel Mode335

13.2.19.4 Debug Mode335

13.3 Overview of the ARM 1022E Processor336

13.3.1 Components of the Processor337

13.3.1.1 Integer Unit338

13.3.2 Registers338

13.3.3 Integer Core338

13.3.4 Integer Core Pipeline339

13.3.4.1 Prefetch Unit339

13.3.4.2 Load/Store Unit342

13.3.5 Memory Management Unit343

13.3.6 Caches and Write Buffer343

13.3.7 Bus Interface344

13.3.8 Topology345

13.3.9 Coprocessor Interface345

13.3.10 Coprocessor Pipeline346

13.3.11 Debug Unit346

13.3.12 Halt Mode346

13.3.13 Monitor Debug-Mode346

13.3.14 Clocking and PLL347

13.3.15 ETM Interface Logic348

13.3.16 Operating States348

13.3.17 Switching State350

13.3.18 Switching State During Exception Handling350

13.3.19 Operating Modes350

CHAPTER 14 TENSILICA CONFIGURABLE IP CORE352

14.0 Introduction:Moore's Law Revisited352

14.1 Chip Design Process354

14.1.1 Building the Wrong Chip354

14.1.2 Fundamental Trends of SoC Design355

14.1.3 A New SoC for Every System is a Bad Idea356

14.1.4 Nanometer Technology357

14.1.5 SoC Design Reform358

14.1.6 SoC Programmability359

14.1.7 Programmability Versus Efficiency360

14.1.8 The Key to SoC Design Success363

14.1.9 An Improved Design Methodology for SoC Design364

14.1.10 The Configurable Processor as a Building Block365

14.1.11 Rapid SoC Development Using Automatically Generated Processors366

14.1.12 The Starting Point:Essential Interfaces and Computation367

14.1.13 Parallelizing a Task367

14.1.14 Implications of Automatic Instruction-Set Generation371

14.2 Tensilica Xtensa Architecture Overview372

14.3 Principles of Instruction Set Design374

14.4 Tensilica Xtensa Processor Uniqueness374

14.5 Registers375

14.6 Instruction Width376

14.7 Compound Instructions377

14.8 Branches378

14.9 Instruction Pipeline380

14.10 Limited Instruction Constant Width381

14.11 Short Instruction Format381

14.12 Register Windows382

14.13 Xtensa LX2 Summary383

CHAPTER 15 DIGITAL SIGNAL PROCESSORS385

15.0 DSP Overview385

15.1 TMS320C55x385

15.1.1 Characteristics of the TMS320C55x386

15.1.1.1 Market Segments387

15.1.1.2 DSP Applications387

15.1.2 Key Features of the C55x387

15.1.3 Instruction Set Architecture388

15.1.3.1 Instruction Pipelining389

15.1.3.2 CPU Features389

15.1.3.3 Instruction Set390

15.1.4 Primary Functional Units390

15.1.4.1 Instruction Buffer Unit391

15.1.4.2 Program Flow Unit393

15.1.4.3 Address Data Flow Unit395

15.1.4.4 Data Computation Unit396

15.1.5 Device Special Features398

15.1.5.1 Low-Power Dissipation398

15.1.6 Low-Power Design398

15.1.6.1 Memory Accesses398

15.1.6.2 Automatic Power Mechanisms398

15.1.6.3 Low-Power Enhancements399

15.1.6.4 Power Conservation399

15.1.6.5 Idle Domains399

15.1.6.6 Advanced Technology399

15.1.7 Processor On-Chip Peripherals400

15.1.7.1 On-Chip Memory400

15.1.7.2 Analog-to-Digital Converter400

15.1.7.3 DSP Clock Generator401

15.1.7.4 DMA Controller401

15.1.7.5 External Memory Interface403

15.1.7.6 I2C Module403

15.1.7.7 Multimedia/SD Card Controller405

15.1.7.8 Programmable Timers405

15.1.7.9 UART405

15.1.7.10 USB Module407

15.1.8 Emulation and Test408

15.2 Analog Devices ADSP-BF535 Blackfin Processor408

15.2.1 Portable Low-Power Architecture409

15.2.2 System Integration409

15.2.3 Processor Core411

15.2.3.1 Instruction Pipeline412

15.2.3.2 Instruction Pipeline Flow412

15.2.4 Memory Architecture413

15.2.4.1 Internal(On-Chip)Memory414

15.2.4.2 PCI415

15.2.4.3 I/O Memory Space415

15.2.5 Event Handling415

15.2.5.1 Core Event Controller(CEC)416

15.2.5.2 System Interrupt Controller(SIC)417

15.2.5.3 Interrupt Event Control417

15.2.6 DMA Controller418

15.2.7 External Memory Control419

15.2.7.1 SDRAM Controller420

15.2.8 Asynchronous Controller420

15.2.9 PCI Interface420

15.2.9.1 PCI Host Functions420

15.2.9.2 PCI Target Function421

15.2.10 USBDevice421

15.2.11 Real-Time Clock421

15.2.12 Watchdog Timer422

15.2.13 Timers422

15.2.14 Serial Ports423

15.2.15 Serial Peripheral Interface(SPI)Ports424

15.2.16 UART Ports425

15.2.17 Dynamic Power Management426

15.2.17.1 Full On Operating Mode426

15.2.17.2 Active Operating Mode426

15.2.17.3 Sleep Operating Mode427

15.2.17.4 Deep Sleep Operating Mode427

15.2.18 Operating Modes and States427

INDEX429