数字设计与Verilog实现 第5版 英文版2025|PDF|Epub|mobi|kindle电子书版本百度云盘下载

数字设计与Verilog实现 第5版 英文版PDF格式电子书版下载

注意：本站所有压缩包均有解压码： 点击下载压缩包解压工具

1 Digital Systemsand Binary Numbers17

1.1 Digital Systems17

1.2 Binary Numbers19

1.3 Number-Base Conversions22

1.4 Octal and Hexadecimal Numbers24

1.5 Complements of Numbers26

1.6 Signed Binary Numbers30

1.7 Binary Codes34

1.8 Binary Storage and Registers43

1.9 Binary Logic46

2 Boolean Algebra and Logic Gates54

2.1 Introduction54

2.2 Basic Definitions54

2.3 Axiomatic Definition of Boolean Algebra56

2.4 Basic Theorems and Properties of Boolean Algebra59

2.5 Boolean Functions62

2.6 Canonical and Standard Forms67

2.7 Other Logic Operations74

2.8 Digital Logic Gates76

2.9 Integrated Circuits82

3 Gate-Level Minimization89

3.1 Introduction89

3.2 The Map Method89

3.3 Four-Variable K-Map96

3.4 Product-of-Sums Simplification100

3.5 Don't-Care Conditions104

3.6 NAND and NOR Implementation106

3.7 Other Two-Level Implementations113

3.8 Exclusive-OR Function119

3.9 Hardware Description Language124

4 Combinational Logic141

4.1 Introduction141

4.2 Combinational Circuits141

4.3 Analysis Procedure142

4.4 Design Procedure145

4.5 Binary Adder-Subtractor149

4.6 Decimal Adder160

4.7 Binary Multiplier162

4.8 Magnitude Comparator164

4.9 Decoders166

4.10 Encoders171

4.11 Multiplexers174

4.12 HDL Models of Combinational Circuits180

5 Synchronou s Sequential Logic206

5.1 Introduction206

5.2 Sequential Circuits206

5.3 Storage Elements:Latches209

5.4 Storage Elements:Flip-Flops212

5.5 Analysis of Clocked Sequential Circuits220

5.6 Synthesizable HDL Models of Sequential Circuits233

5.7 State Reduction and Assignment247

5.8 Design Procedure252

6 Registers and Counters271

6.1 Registers271

6.2 Shift Registers274

6.3 Ripple Counters282

6.4 Synchronous Counters287

6.5 Other Counters294

6.6 HDL for Registers and Counters299

7 Memory and Programmable Logic315

7.1 Introduction315

7.2 Random-Access Memory316

7.3 Memory Decoding323

7.4 Error Detection and Correction328

7.5 Read-Only Memory331

7.6 Programmable Logic Array337

7.7 Programmable Array Logic341

7.8 Sequential Programmable Devices345

8 Design at the Register Transfer Level367

8.1 Introduction367

8.2 Register Transfer Level Notation367

8.3 Register Transfer Levelin HDL370

8.4 Algorithmic State Machines（ASMs）379

8.5 Design Example （ASMD Chart）387

8.6 HDL Description of Design Example397

8.7 Sequential Binary Multiplier407

8.8 Control Logic412

8.9 HDL Description of Binary Multiplier418

8.10 Design with Multiplexers427

8.11 Race-Free Design（Software Race Conditions）438

8.12 Latch-Free Design（Why Waste Silicon？）441

8.13 Other Language Features442

9 Laboratory Experiments with Standard ICs and FPGAs454

9.1 Introduction to Experiments454

9.2 Experiment 1:Binary and Decimal Numbers459

9.3 Experiment 2:Digital Logic Gates462

9.4 Experiment 3:Simplification of Boolean Functions464

9.5 Experiment 4:Combinational Circuits466

9.6 Experiment 5:Code Converters468

9.7 Experiment 6:Design with Multiplexers469

9.8 Experiment 7:Adders and Subtractors471

9.9 Experiment 8:Flip-Flops473

9.10 Experiment 9:Sequential Circuits476

9.11 Experiment 10:Counters477

9.12 Experiment 11:Shift Registers479

9.13 Experiment 12:Serial Addition482

9.14 Experiment 13:Memory Unit483

9.15 Experiment 14:Lamp Handball485

9.16 Experiment 15:Clock-Pulse Generator489

9.17 Experiment 16:Parallel Adder and Accumulator491

9.18 Experiment 17:Binary Multiplier494

9.19 Verilog HDL Simulation Experiments and Rapid Prototyping with FPGAs496

10 Standard Graphic Symbols504

10.1 Rectangular-Shape Symbols504

10.2 Qualifying Symbols507

10.3 Dependency Notation509

10.4 Symbols for Combinational Elements511

10.5 Symbols for Flip-Flops513

10.6 Symbols for Registers515

10.7 Symbols for Counters518

10.8 Symbol for RAM520

Appendix523

Answers to Selected Problems537

Index555