结构化计算机组成 英文版2025|PDF|Epub|mobi|kindle电子书版本百度云盘下载

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PREFACE1

1 INTRODUCTION1

1.1 STRUCTURED COMPUTER ORGANIZATION2

1.1.1 Languages, Levels, and Virtual Machines2

1.1.2 Contemporary Multilevel Machines4

1.1.3 Evolution of Multilevel Machines8

1.2 MILESTONES IN COMPUTER ARCHITECTURE13

1.2.1 The Zeroth Generation--Mechanical Computers (1642-1945)13

1.2.2 The First Generation--Vacuum Tubes (1945-1955)16

1.2.3 The Second Generation--Transistors (1955-1965)19

1.2.4 The Third Generation--Integrated Circuits (1965-1980)21

1.2.5 The Fourth Generation--Very Large Scale Integration (1980-?)23

1.3 THE COMPUTER ZOO24

1.3.1 Technological and Economic Forces25

1.3.2 The Computer Spectrum26

1.4.1 Introduction to the Pentium II29

1.4 EXAMPLE COMPUTER FAMILIES29

1.4.2 Introduction to the UltraSPARC II31

1.4.3 Introduction to the picoJava II34

1.5 OUTLINE OF THIS BOOK36

2 COMPUTER SYSTEMS ORGANIZATION39

2.1 PROCESSORS39

2.1.1 CPU Organization40

2.1.2 Instruction Execution42

2.1.3 RISC versus CISC46

2.1.4 Design Principles for Modern Computers47

2.1.5 Instruction-Level Parallelism49

2.1.6 Processor-Level Parallelism53

2.2 PRIMARY MEMORY56

2.2.1 Bits56

2.2.2 Memory Addresses57

2.2.3 Byte Ordering58

2.2.4 Error-Correcting Codes61

2.2.5 Cache Memory65

2.2.6 Memory Packaging and Types67

2.3 SECONDARY MEMORY68

2.3.1 Memory Hierarchies69

2.3.2 Magnetic Disks70

2.3.3 Floppy Disks73

2.3.4 IDE Disks73

2.3.5 SCSI Disks75

2.3.6 RAID76

2.3.7 CD-ROMs80

2.3.8 CD-Recordables84

2.3.9 CD-Rewritables86

2.3.10 DVD86

2.4 INPUT/OUTPUT89

2.4.1 Buses89

2.4.2 Terminals91

2.4.3 Mice99

2.4.4 Printers101

2.4.5 Modems106

2.4.6 Character Codes109

2.5 SUMMARY113

3 THE DIGITAL LOGIC LEVEL117

3.1 GATES AND BOOLEAN ALGEBRA117

3.1.1 Gates118

3.1.2 Boolean Algebra120

3.1.3 Implementation of Boolean Functions122

3.1.4 Circuit Equivalence123

3.2.1 Integrated Circuits128

3.2 BASIC DIGITAL LOGIC CIRCUITS128

3.2.2 Combinational Circuits129

3.2.3 Arithmetic Circuits134

3.2.4 Clocks139

3.3 MEMORY141

3.3.1 Latches141

3.3.2 Flip-Flops143

3.3.3 Registers145

3.3.4 Memory Organization146

3.3.5 Memory Chips150

3.3.6 RAMs and ROMs152

3.4 CPU CHIPS AND BUSES154

3.4.1 CPU Chips154

3.4.2 Computer Buses156

3.4.3 Bus Width159

3.4.4 Bus Clocking160

3.4.5 Bus Arbitration165

3.4.6 Bus Operations167

3.5 EXAMPLE CPU CHIPS170

3.5.1 The Pentium II170

3.5.2 The UltraSPARC II176

3.5.3 The picoJava II179

3.6 EXAMPLE BUSES181

3.6.1 The ISA Bus181

3.6.2 The PCI Bus183

3.6.3 The Universal Serial Bus189

3.7.1 I/O Chips193

3.7 INTERFACING193

3.7.2 Address Decoding195

3.8 SUMMARY198

4 THE MICROARCHITECTURE LEVEL203

4.1 AN EXAMPLE MICROARCHITECTURE203

4.1.1 The Data Path204

4.1.2 Microinstructions211

4.1.3 Microinstruction Control: The Mic-l213

4.2 AN EXAMPLE ISA: IJVM218

4.2.1 Stacks218

4.2.2 The IJVM Memory Model220

4.2.3 The IJVM Instruction Set222

4.2.4 Compiling Java to IJVM226

4.3 AN EXAMPLE IMPLEMENTATION227

4.3.1 Microinstructions and Notation227

4.3.2 Implementation of IJVM Using the Mic-1232

4.4.1 Speed versus Cost243

4.4 DESIGN OF THE MICROARCHITECTURE LEVEL243

4.4.2 Reducing the Execution Path Length245

4.4.3 A Design with Prefetching: The Mic-2253

4.4.4 A Pipelined Design: The Mic-3253

4.4.5 A Seven-Stage Pipeline: The Mic-4260

4.5 IMPROVING PERFORMANCE264

4.5.1 Cache Memory265

4.5.2 Branch Prediction270

4.5.3 Out-of-Order Execution and Register Renaming276

4.5.4 Speculative Execution281

4.6 EXAMPLES OF THE MICROARCHITECTURE LEVEL283

4.6.1 The Microarchitecture of the Pentium II CPU283

4.6.2 The Microarchitecture of the UltraSPARC-II CPU288

4.6.3 The Microarchitecture of the picoJava II CPU291

4.6.4 A Comparison of the Pentium, UltraSPARC, and picoJava296

4.7 SUMMARY298

5 THE INSTRUCTION SET ARCHITECTURE LEVEL303

5.1.1 Properties of the ISA Level305

5.1 OVERVIEW OF THE ISA LEVEL305

5.1.2 Memory Models307

5.1.3 Registers309

5.1.4 Instructions311

5.1.5 Overview of the the Pentium II ISA Level311

5.1.6 Overview of the the UltraSPARC II ISA Level313

5.1.7 Overview of the Java Virtual Machine317

5.2 DATA TYPES318

5.2.1 Numeric Data Types319

5.2.2 Nonnumeric Data Types319

5.2.3 Data Types on the Pentium II320

5.2.4 Data Types on the UltraSPARC II321

5.2.5 Data Types on the Java Virtual Machine321

5.3 INSTRUCTION FORMATS322

5.3.1 Design Criteria for Instruction Formats322

5.3.2 Expanding Opcodes325

5.3.3 The Pentium II Instruction Formats327

5.3.4 The UltraSPARC II Instruction Formats328

5.3.5 The JVM Instruction Formats330

5.4 ADDRESSING332

5.4.1 Addressing Modes333

5.4.2 Immediate Addressing334

5.4.3 Direct Addressing334

5.4.4 Register Addressing334

5.4.5 Register Indirect Addressing335

5.5.6 Indexed Addressing336

5.5.8 Stack Addressing338

5.5.7 Based-Indexed Addressing338

5.5.9 Addressing Modes for Branch Instructions341

5.5.10 Orthogonality of Opcodes and Addressing Modes342

5.5.11 The Pentium II Addressing Modes344

5.5.12 The UltraSPARC II Addressing Modes346

5.5.13 The JVM Addressing Modes346

5.5.14 Discussion of Addressing Modes347

5.5.1 Data Movement Instructions348

5.5 INSTRUCTION TYPES348

5.5.2 Dyadic Operations349

5.5.3 Monadic Operations350

5.5.4 Comparisons and Conditional Branches352

5.5.5 Procedure Call Instructions353

5.5.6 Loop Control354

5.5.7 Input/Output356

5.5.8 The Pentium II Instructions359

5.5.9 The UltraSPARC II Instructions362

5.5.10 The PicoJava II Instructions364

5.5.11 Comparison of Instruction Sets369

5.6 FLOW OF CONTROL370

5.6.1 Sequential Flow of Control and Branches371

5.6.2 Procedures372

5.6.3 Coroutines376

5.6.4 Traps379

5.6.5 Interrupts379

5.7 A DETAILED EXAMPLE: THE TOWERS OF HANOI383

5.7.1 The Towers of Hanoi in Pentium II Assembly Language384

5.7.2 The Towers of Hanoi in UltraSPARC II Assembly Language384

5.7.3 The Towers of Hanoi in JVM Assembly Language386

5.8 THE INTEL IA-64388

5.8.1 The Problem with the Pentium II390

5.8.2 The IA-64 Model: Explicitly Parallel Instruction Computing391

5.8.3 Predication393

5.8.4 Speculative Loads395

5.8.5 Reality Check396

5.9 SUMMARY397

6 THE OPERATING SYSTEM MACHINE LEVEL403

6.1 VIRTUAL MEMORY404

6.1.1 Paging405

6.1.2 Implementation of Paging407

6.1.3 Demand Paging and the Working Set Model409

6.1.4 Page Replacement Policy412

6.1.5 Page Size and Fragmentation414

6.1.6 Segmentation415

6.1.7 Implementation of Segmentation418

6.1.8 Virtual Memory on the Pentium II421

6.1.9 Virtual Memory on the UltraPSARC426

6.1.10 Virtual Meory and Caching428

6.2 VIRTUAL I/O INSTRUCTIONS429

6.2.1 Files430

6.2.2 Implementation of Virtual I/O Instructions431

6.2.3 Directory Management Instructions435

6.3 VIRTUAL INSTRUCTIONS FOR PARALLEL PROCESSING436

6.3.1 Process Creation437

6.3.2 Race Conditions438

6.3.3 Process Synchronization Using Semaphores442

6.4 EXAMPLE OPERATING SYSTEMS446

6.4.1 Introduction446

6.4.2 Examples of Virtual Memory455

6.4.3 Examples of Virtual I/O459

6.4.4 Examples of Process Management470

6.5 SUMMARY476

7 THE ASSEMBLY LANGUAGE LEVEL483

7.1 INTRODUCTION TO ASSEMBLY LANGUAGE484

7.1.1 What Is an Assembly Language?484

7.1.2 Why Use Assembly Language?485

7.1.3 Format of an Assembly Language Statement488

7.1.4 Pseudoinstructions491

7.2 MACROS494

7.2.1 Macro Definition, Call, and Expansion494

7.2.2 Macros with Parameters496

7.2.3 Advanced Features497

7.2.4 Implementation of a Macro Facility in an Assembler498

7.3 THE ASSEMBLY PROCESS498

7.3.1 Two-Pass Assemblers498

7.3.2 Pass One499

7.3.3 Pass Two502

7.3.4 The Symbol Table505

7.4 LINKING AND LOADING506

7.4.1 Tasks Performed by the Linker508

7.4.2 Structure of an Object Module511

7.4.3 Binding Time and Dynamic Relocation512

7.4.4 Dynamic Linking515

7.5 SUMMARY519

8 PARALLEL COMPUTER ARCHITECTURES523

8.1 DESIGN ISSUES FOR PARALLEL COMPUTERS524

8.1 Communication Models526

8.1.2 Interconnection Networks530

8.1.3 Performance539

8.1.4 Software545

8.1.5 Taxonomy of Parallel Computers551

8.2 SIMD COMPUTERS554

8.2.1 Array Processors554

8.2.2 Vector Processors555

8.3.1 Memory Semantics559

8.3 SHARED-MEMORY MULTIPROCESSORS559

8.3.2 UMA Bus-Based SMP Architectures564

8.3.3 UMA Multiprocessors Using Crossbar Switches569

8.3.4 UMA Multiprocessors Using Multistage Switching Networks571

8.3.5 NUMA Multiprocessors573

8.3.6 Cache coherent NUMA Multiprocessors575

8.3.7 COMA Multiprocessors585

8.4 MESSAGE-PASSING MULTICOMPUTERS586

8.4.1 MPPs-Massively Parallel Processors587

8.4.2 COWs-Clusters of Workstations592

8.4.3 Scheduling593

8.4.4 Communication Software for Multicomputers598

8.4.5 Application-Level Shared Memory601

8.5 SUMMARY609

9 READING LIST AND BIBLIOGRAPHY613

9.1 SUGGESTIONS FOR FURTHER READING613

9.1.1 Introduction and General Works613

9.1.2 Computer Systems Organization614

9.1.3 The Digital Logic Level615

9.1.4 The Microarchitecture Level616

9.1.5 The Instruction Set Architecture Level617

9.1.6 The Operating System Machine Level617

9.1.7 The Assembly Language Level618

9.1.8 Parallel Computer Architectures618

9.1.9 Binary and Floating-Point Numbers620

9.2 ALPHABETICAL BIBLIOGRAPHY620

A.1 FINITE-PRECISION NUMBERS631

A BINARY NUMBERS631

A.2 RADIX NUMBER SYSTEMS633

A.3 CONVERSION FROM ONE RADIX TO ANOTHER635

A.4 NEGATIVE BINARY NUMBERS637

A.5 BINARY ARITHMETIC640

B FLOATING-POINT NUMBERS643

B.1 PRINCIPLES OF FLOATING POINT644

INDEX653

B.2 IEEE FLOATING-POINT STANDARD754