CMOS锁相环 分析和设计2025|PDF|Epub|mobi|kindle电子书版本百度云盘下载

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1 Introduction1

1.1 MOTIVATION1

1.2 SUMMARY OF BOOK2

1.3 BOOK ORGANIZATION4

REFERENCES5

2 Frequency Synthesizer for Wireless Applications7

2.1 DEFINITION AND CHARACTERISTICS7

2.2 PHASE NOISE AND TIMING JITTER8

2.2.1 Phase noise and spurious tone8

2.2.2 Timing jitter11

2.3 IMPLEMENTATION OF FREQUENCY SYNTHESIZER14

2.3.1 Direct analog frequency synthesizer14

2.3.2 Direct digital frequency synthesizer15

2.3.3 PLL-based frequency synthesizer16

2.3.4 DLL-based frequency synthesizer20

2.3.5 Hybrid frequency synthesizer21

2.3.6 Summary and comparison of synthesizers21

2.4 FREQUENCY SYNTHESIZER FOR WIRELESS TRANSCEIVERS22

2.5 OTHER APPLICATIONS OF PLL AND FREQUENCY SYNTHESIZER24

REFERENCES26

3 PLL Frequency Synthesizer31

3.1 PLL FREQUENCY SYNTHESIZER BASICS31

3.1.1 Basic building blocks of charge-pump PLL31

3.1.2 Continuous-time linear phase analysis34

3.1.3 Locking time44

3.1.4 Tracking and acquisition56

3.2 FAST-LOCKING TECHNIQUES58

3.2.1 Bandwidth gear-shifting58

3.2.2 VCO pre-tuning60

3.3 DISCRETE-TIME ANALYSIS AND NONLINEAR MODELING60

3.3.1 z-domain transfer function and stability analysis60

3.3.2 Nonlinear dynamic behavior modeling62

3.4 DESIGN EXAMPLE：2.4GHz INTEGER-N PLL FOR BLUETOOTH62

REFERENCES65

4 ∑△ Fractional-N PLL Synthesizer69

4.1 ∑△ FRACTIONAL-N FREQUENCY SYNTHESIZER69

4.1.1 ∑△ quantization noise to phase noise mapping70

4.1.2 ∑△ quantization noise to timing jitter mapping73

4.2 A COMPARATIVE STUDY OF DIGITAL ∑△ MODULATORS73

4.2.1 Design considerations73

4.2.2 Four types of digital ∑△ modulators74

4.2.3 Summary of comparative study87

4.3 OTHER APPLICATIONS OF ∑△-PLL90

4.3.1 Direct digital modulation90

4.3.2 Frequency-to-digital conversion91

4.4 MODELING AND SIMULATION OF ∑△-PLL92

4.5 DESIGN EXAMPLE：900MHz ∑△-PLL FOR GSM95

REFERENCES98

5 Enhanced Phase Switching Prescaler103

5.1 PRESCALER ARCHITECTURE103

5.1.1 Conventional prescaler103

5.1.2 Phase switching prescaler105

5.1.3 Injection-locked prescaler107

5.1.4 Summary and comparison of prescalers107

5.2 ENHANCED PHASE-SWITCHING PRESCALER108

5.3 CIRCUIT DESIGN AND SIMULATION RESULTS110

5.3.1 Eight 45°-spaced phases generation110

5.3.2 8-to-1 multiplexer111

5.3.3 Switching control circuit112

5.3.4 Asynchronous frequency divider113

5.4 DELAY BUDGET IN THE SWITCHING CONTROL LOOP115

5.5 SPURS DUE TO NONIDEAL 45° PHASE SPACING117

REFERENCES123

6 Loop Filter With Capacitance Multiplier127

6.1 LOOP FILTER ARCHITECTURE127

6.1.1 Passive loop filter127

6.1.2 Dual-path loop filter128

6.1.3 Sample-reset loop filter131

6.1.4 Other loop filter architectures133

6.1.5 Summary and comparison of loop filters137

6.2 LOOP FILTER AND CHARGE-PUMP NOISE MAPPING138

6.3 LOOP FILTER WITH CAPACITANCE MULTIPLIER141

6.3.1 Third-order passive loop filter141

6.3.2 Capacitance multiplier142

6.3.3 Simulation of loop filter with capacitance multiplier145

6.3.4 Noise consideration148

REFERENCES149

7 Other Building Blocks of PLL151

7.1 VCO151

7.1.1 LC-VCO151

7.1.2 Varactor152

7.1.3 Inductor155

7.1.4 VCO phase noise156

7.1.5 Layout161

7.2 PHASE-FREQUENCY DETECTOR162

7.3 CHARGE-PUMP164

7.3.1 Reference spur164

7.3.2 Charge pump architectures171

7.4 PROGRAMMABLE DIVIDER173

7.5 DIGITAL ∑△ MODULATOR176

7.6 CHIP LAYOUT176

REFERENCES178

8 Prototype Measurement Results183

8.1 PRESCALER MEASUREMENT183

8.2 LOOP FILTER MEASUREMENT186

8.3 PLL MEASUREMENT188

REFERENCES194

9 Conclusions195

Appendix199

Index213